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Article: TSMC and Cadence Tackle Low Power Challenges at 90 Nanometers and below with New TSMC Reference Flow.
- Article from:
- Business Wire
- Article date:
- June 7, 2004
CopyrightCOPYRIGHT 2004 Business Wire. This material is published under license from the publisher through the Gale Group, Farmington Hills, Michigan. All inquiries regarding rights should be directed to the Gale Group. (Hide copyright information)
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Business Editors/High-Tech Writers
SAN DIEGO--(BUSINESS WIRE)--June 7, 2004
Cadence Encounter and Allegro Platforms Provide Complete Power Closure
and Chip-Package Co-Design Solutions for TSMC Reference Flow 5.0
Cadence Design Systems, Inc. (NYSE:CDN) today announced the integration of the Cadence(R) Encounter(TM) digital IC design platform and the Cadence(R) Allegro(R) system interconnect design platform into TSMC's Reference Flow 5.0. This reference flow includes key Cadence technologies for low power design and chip-package design that enable higher productivity and improved design quality. Supporting designs targeting TSMC's ...