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Article: Sign-off power network and electromigration-analysis tool decrease delay from voltage drop.(leading edge)
- Article from:
- EDN
- Article date:
- May 26, 2005
- Author:
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SYNOPSYS HAS COMBINED static- and dynamic-timing-analysis technologies to create PrimeRail, a tool it bets will become the sign-off tool for gate-level power-network analysis and transistor-level EM (electromigration) analysis. Rajiv Maheshwary, senior director of sign-off and power products at Synopsys, says that, as voltage drop becomes more common in large designs, it is having a greater impact on overall performance of ASICs and SOCs (systems on chips).
"Voltage drop is an increasing part of overall delay," says Maheshwary. "At 90-nm processes, 10% of overall delay is a result of voltage drop, and, at 65 nm, it can be as much as 15%. A few years ago when ...