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Article: Synopsys Announces EDA Industry's First Verification IP Library for SystemVerilog With Methodology Support.
- Article from:
- PR Newswire
- Article date:
- March 20, 2006
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VCS Verification Library Enables Rapid Adoption of SystemVerilog With Full Support of the Verification Methodology Manual (VMM) for SystemVerilog
MOUNTAIN VIEW, Calif., March 20 /PRNewswire-FirstCall/ -- Synopsys, Inc. , a world leader in semiconductor design software, today announced that its VCS(R) Verification Library, containing DesignWare(R) verification intellectual property (VIP), is first to support testbenches created using IEEE Std 1800(TM)-2005 SystemVerilog and the coverage-driven methodology defined in the Verification Methodology Manual (VMM) for SystemVerilog, published by Springer Science+Business Media. Verification engineers who use ...