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Article: Fetch unit design for scalable simultaneous multithreading (ScSMT).
- Article from:
- Journal of Computer Science & Technology
- Article date:
- May 1, 2001
- Author:
CopyrightCOPYRIGHT 2001 Graduate Network of Argentine Universities with Computer Science Schools (RedUNCI). This material is published under license from the publisher through the Gale Group, Farmington Hills, Michigan. All inquiries regarding rights should be directed to the Gale Group. (Hide copyright information)
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Abstract. Continuous IC process enhancements make possible to integrate on a single chip the resources required for simultaneously executing multiple control flows or threads, exploiting different levels of thread-level parallelism: application-, function-, and loop-level. Scalable simultaneous multithreading combines static and dynamic mechanisms to assemble a complexity-effective design that provides high instruction per cycle rates without sacrificing cycle time nor single-thread performance.
This paper addresses the design of the fetch unit for a high-performance, scalable, simultaneous multithreaded processor. We present the detailed microarchitecture of a ...
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