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Article: Design procedure based on VHDL language transformations.(VHSIC (very high speed integrated circuit) hardware description language)
- Article from:
- VLSI Design
- Article date:
- January 1, 2002
- Author:
CopyrightCOPYRIGHT 2002 Hindawi Publishing Corp. This material is published under license from the publisher through the Gale Group, Farmington Hills, Michigan. All inquiries regarding rights should be directed to the Gale Group. (Hide copyright information)
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One of the major problems within the VHDL based behavioral synthesis is to start the design on higher abstraction level than the register transfer level (RTL). VHDL semantics was designed strictly for simulation, therefore it was not considered as high-level synthesis language. A novel synthesis procedure was developed, which uses the methodology of high level synthesis. It starts from an abstract VHDL model and produces an RTL VHDL description through successive language transformations while preserving the VHDL standard simulation semantics. The steps of the synthesis do not use graph representation or other meta-language, but apply the standard VHDL only. This VHDL ...
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Article: GenRad announces VHDL Interface to System HILO.
PR Newswire;
June 7, 1989 ;
700+ words
...GENRAD ANNOUNCES VHDL INTERFACE TO SYSTEM HILO CONCORD, Mass ... Inc. (NYSE: GEN) announced yesterday VHDL (VHSIC Hardware Description Language ... Logic Simulation Toolkit. The new GenRad VHDL Interface converts VHDL hardware descriptions ...
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