Article: Atrenta Gains Key Patents for Chip Design Analysis Technologies.

Patents Awarded:

-- Method for Determining Fault Coverage from RTL Description

-- An Apparatus and Method for Handling of Multi-Level Circuit Design Data

-- Method for Efficient Identification and Implementation of Clock Gating of Integrated Circuits

-- Automatic Assertion Generation for Functional Validation of Integrated Circuits

-- Method, System, and Computer Program Product for Automatic Insertion and Correctness Verification of Level Shifters in Integrated Circuits with Multiple Voltage Domains

SAN JOSE, Calif. -- Strengthening its leadership position in early design analysis tools, Atrenta, today announced ...

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