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Article: Self-test for FPGAs and CPLDs requires no overhead. (Field Programmable Gate Arrays; Circuit Programmable Logic Designs)
- Article from:
- EDN
- Article date:
- November 6, 1997
- Author:
CopyrightCOPYRIGHT 1997 Reed Business Information, Inc. (US). This material is published under license from the publisher through the Gale Group, Farmington Hills, Michigan. All inquiries regarding rights should be directed to the Gale Group. (Hide copyright information)
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The intricacy of FPGAs and CPLDs means that you need to test them both at the system-manufacturing level and in the field. Traditionally, these tests require application-specific test patterns for in-circuit board testing and offline system-diagnostic-software routines for field testing. Developing these test patterns and diagnostic routines can be time-consuming and costly, particularly when the system is difficult to test.
Manufacturers often have comprehensive device-level FPGA and CPLD tests to check all possible modes of operation of the programmable logic, as well as to detect faults affecting the programmable-interconnect network. However, you cannot reuse ...
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Article: Patent No. 7,579,864 Issued on Aug. 25, Assigned to Panasonic for ...
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... ... Takahiro Ichinomiya, Osaka, Japan, has developed a logic block control system. The inventor was issued U.S. Patent No ... are stopped. As a technique of stopping an operation of a logic block, a gated clock technique, a power-off technique, or the ...
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