|
|
Article: United States : Tiempo Chooses Verific Design Automation`s SystemVerilog Front End.
- Article from:
- TendersInfo
- Article date:
- October 29, 2009
CopyrightCOPYRIGHT 2009 Al Bawaba (Middle East) Ltd. This material is published under license from the publisher through the Gale Group, Farmington Hills, Michigan. All inquiries regarding rights should be directed to the Gale Group. (Hide copyright information)
|
Byline: Mamta03
Tiempo, provider of breakthrough, ultra low-power asynchronous intellectual
property (IP) for embedded applications, has chosen Verific Design Automation, a de facto industry standard, as the front end for its software products.
Tiempo licenses Verific`s SystemVerilog analyzer and static elaborator to serve as the front end to its Asynchronous Circuit Compiler (ACC), synthesis software that generates asynchronous and delay-insensitive circuits from a model written in SystemVerilog.
"Verific`s software serves as an essential component of our product development plan and gave us an immediate head start on worldwide ...