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Article: Tiempo Chooses Verific Design Automation's SystemVerilog Front End.
- Article from:
- Electronics Newsweekly
- Article date:
- November 11, 2009
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Tiempo, provider of breakthrough, ultra low-power asynchronous intellectual property (IP) for embedded applications, has chosen Verific Design Automation, a de facto industry standard, as the front end for its software products.
Tiempo licenses Verific's SystemVerilog analyzer and static elaborator to serve as the front end to its Asynchronous Circuit Compiler (ACC), synthesis software that generates asynchronous and delay-insensitive circuits from a model written in SystemVerilog.
"Verific's software serves as an essential component of our product development plan and gave us an immediate head start on worldwide product deployment," remarks Serge ...