|
|
Article: SEMATECH Reports New Approach to Simulate Transistor Noise: Accelerates Development of Advanced Device Processing.
- Article from:
- Electronics Newsweekly
- Article date:
- November 11, 2009
CopyrightCOPYRIGHT 2009 NewsRX. This material is published under license from the publisher through the Gale Group, Farmington Hills, Michigan. All inquiries regarding rights should be directed to the Gale Group. (Hide copyright information)
|
Researchers from SEMATECH's Front End Processes (FEP) program have developed a comprehensive transistor noise model capable of extracting defect characteristics from low frequency noise data in advanced gate stack transistors using both conventional and novel dielectrics. The proposed model is a key step towards identifying and minimizing defects to support aggressive device scaling. SEMATECH's results were presented at the IEEE Integrated Reliability Workshop (IRW) on Thursday, October 22, in Lake Tahoe, CA.
Low frequency noise - random fluctuations in device current - is a growing concern in the performance of integrated CMOS circuits, particularly as the ...