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Article: PCB-layout techniques for gigasample ADCs.
- Article from:
- EDN
- Article date:
- November 12, 2009
CopyrightCOPYRIGHT 2009 Reed Business Information, Inc. (US). This material is published under license from the publisher through the Gale Group, Farmington Hills, Michigan. All inquiries regarding rights should be directed to the Gale Group. (Hide copyright information)
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By Edison Fong, National Semiconductor
When a multilayer board operates at speeds greater than a few hundred megahertz, it's a challenge to maintain signals without mismatches, losses, distortion, or EMI. Follow these guidelines for PCB layout to preserve signal integrity and achieve high-speed performance.
As a general rule, when a design's speed rises to more than a few hundred megahertz, it requires a PCB (printed-circuit board) with four or more layers. The only exception occurs when the design uses small boards; in that case, a two-layer board may be acceptable. Developers typically perform these designs on evaluation boards for baluns, chip ...