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Article: Static column decode speeds up DRAM access time. (includes related article on designing a memory timer) (technical)
- Article from:
- EDN
- Article date:
- March 2, 1989
- Author:
CopyrightCOPYRIGHT 1989 Reed Business Information, Inc. (US). This material is published under license from the publisher through the Gale Group, Farmington Hills, Michigan. All inquiries regarding rights should be directed to the Gale Group. (Hide copyright information)
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Static column decode speeds up DRAM access time
If you're designing a system based on a high-speed 32-bit [mu]P like Motorola's 68020, you'll enjoy clock frequencies greater than 16 MHz and an addressing range of 4G bytes. But a fast clock speed and a large physical addressing range don't necessarily guarantee better performance. Memory access time, not processor speed, may be the deciding factor: If a processor must wait for data from its storage devices, its speed is clearly dependent on the memory bandwidth. And static column decoding can be a useful alternative to cache memory in some situations.
Cache memory is a popular solution for increasing the ...