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Santarini, Michael. "Structured ASICs deserve serious attention at 90nm: the cost of 90nm--not to mention 65nm--silicon is outrageous. Users should take a long, hard look at structured ASICs when considering which fabric to use their next logic design.(design feature)." EDN Asia. Canon Communications L.L.C. 2005. HighBeam Research. 22 Apr. 2018 <https://www.highbeam.com>.
Santarini, Michael. "Structured ASICs deserve serious attention at 90nm: the cost of 90nm--not to mention 65nm--silicon is outrageous. Users should take a long, hard look at structured ASICs when considering which fabric to use their next logic design.(design feature)." EDN Asia. 2005. HighBeam Research. (April 22, 2018). https://www.highbeam.com/doc/1G1-137966777.html
Santarini, Michael. "Structured ASICs deserve serious attention at 90nm: the cost of 90nm--not to mention 65nm--silicon is outrageous. Users should take a long, hard look at structured ASICs when considering which fabric to use their next logic design.(design feature)." EDN Asia. Canon Communications L.L.C. 2005. Retrieved April 22, 2018 from HighBeam Research: https://www.highbeam.com/doc/1G1-137966777.html
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Four years after ASIC vendors introduced their first structured-ASIC devices in response to FPGA vendors eating up their market share, the structured-ASIC market has yet to become a popular choice for logic designs.
But analysts say that the structured-ASIC market is a viable business today and may exceed $1 billion by 2008, as designers add up the cost of 90nm ASIC design and run up against the hard limitations of FPGAs.
Analysts and structured-ASIC vendors put up good arguments about why you should at least consider structured fabric for your next IC-design project. But you should consider a number of variables--both technical and business--when evaluating FPGAs, structured ASICs, and cell-based ASICs.
Companies market structured ASICs as the mid-volume, mid-price missing link between fast-turnaround, reprogrammable but low-volume FPGAs and high-cost, high-volume, hard-to-design cell-based ASICs.
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A structured device resembles a gate array on steroids. Like gate arrays, structured ASICs have a limited number of designable layers (usually one to six), a low tool and NRE cost, and a turnaround time ranging from days to months. As with gate arrays, silicon vendors have taken care of most of the nasty physical-design effects with prerouted and pretested layers. In most devices, they've also predesigned the clock tree. But structured-ASIC devices offer much larger designable gate counts and much more on-chip memory than gate arrays.
A viable market?
The structured-ASIC market has not yet seen widespread adoption among users and has not yet become the $300 million market many proponents had predicted. FPGA proponent Tom Hart, CEO of Quicklogic, goes so far as to say, "Structured ASIC is the last dying gasp of the ASIC business," and John East, president and CEO of Actel, says that structured ASIC "suffers from the same drawbacks that have caused ASICs to lose market share to programmable devices over the past two decades."
Many analysts, however, disagree with Hart's and East's assessments of the structured-ASIC market, saying that FPGAs, structured ASICs, and cell-based ASICs all have unique functions and their own place in the logic-device market.
"This is not about who is going to win," says Semico Research Corp's senior ASIC and SOC (system-on-chip) analyst Richard Wawrzyniak. "It is about what combinations of features and functions, power, time to market, and cost best suit your needs."
Although the structured-ASIC market posted 2004 revenue ranging from only $86 million (iSuppli) to $209 million (In-Stat), not $300 million as previously expected, the market, say analysts, shows signs of picking up (Figure 1).
[FIGURE 1 OMITTED]
Research company IBS Inc predicts that by 2007, one-third of all ASICs will employ structured-ASIC fabric. Bryan Lewis, research vice president and chief semiconductor analyst at Gartner, more or less concurs.
"By 2008, structured ASIC will be about a third of the designs out there, but the revenue is less than 10% of the overall ASIC market," he says. "For a structured ASIC, the typical revenue per design is running around $3 million or $4 million, and in a traditional ASIC, it is running at $5 million or $6 million."
Lewis believes that the structured-array market, which in 2004 was worth $104 million, will become a $1.45 billion market by 2008, with design starts moving from 181 in 2004 to 1230 by 2008. He believes Altera and LSI Logic are currently the structured-ASIC market leaders. He says most structured-ASIC vendors, with the exception of Altera, have been tightlipped when asked about revenue. He notes that Altera reported $19 million in revenue from its HardCopy structured family in 2004. Altera was the only company to provide tapeout and customer data for Table 1.
Alain Bismuth, vice president of the HardCopy product group at Altera, says that the company's customer base for HardCopy has increased from 20 to 30 customers over the last year and that there were 12 design starts in 2003 and 20 in 2004. …
EDN; July 7, 2005
EDN Asia; May 1, 2006
Microwave Journal; September 1, 2004
Semiconductor International; October 1, 2004
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